Semiconductor integrated circuits are normally designed in view of process variations in forming the circuits. Specifically, process variations are presumed, and semiconductor integrated circuits are designed such that they will operate reliably for desired performance within the presumed range of process variation. However, since it is difficult to presume device performance variations, the period of time required to design semiconductor integrated circuits is increased, and it is necessary to give timing margins to allow semiconductor integrated circuits to operate in worst cases. The semiconductor integrated circuits thus designed tend to suffer performance reductions. There have recently been proposed variation compensation circuits capable of compensating for device performance variations of semiconductor integrated circuits to enable the semiconductor integrated circuits to exhibit a constant performance level.
Threshold voltage variation of FETs is a typical type of device performance variation that occurs due to, e.g., rapid thermal anneal (RTA) intra-die variations. As the device manufacturing variations are the result of physical configuration variations and chemical compositions of the semiconductor devices, these variations essentially cannot be avoided because manufacturing errors cannot fully be eliminated.
Current mirrors are often utilized in analog circuits to precisely reproduce reference voltages and currents in areas around and within a chip. While threshold voltage (Vt) must be matched across the chip, long-range Vt mismatches are known to exist due to long-range intra-die process variation from RTA. Known solutions try to keep the local environment of transistors as identical as possible and employ physically large transistors in an effort to minimize mismatch. As these long range mismatch solutions are generally required to act on a very large area, these solutions have been found to be prohibitively expensive.